RASC Reconfigurable Application Specific Computing
Acronym Definition
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Reconfigurable computing is computer processing with very flexible high speed
computing fabrics. The principal difference when compared to using ordinary
microprocessors is the ability to make substantial changes to the data path
itself in addition to the control flow.
History and properties
The concept of reconfigurable computing has existed since the 1960s, when Gerald
Estrin's landmark paper proposed the concept of a computer made of a standard
processor and an array of “reconfigurable” hardware. The main processor would
control the behavior of the reconfigurable hardware. The latter would then be
tailored to perform a specific task, such as image processing or pattern
matching, as quickly as a dedicated piece of hardware. Once the task was done,
the hardware could be adjusted to do some other task. This resulted in a hybrid
computer structure combining the flexibility of software with the speed of
hardware; unfortunately this idea was far ahead of its time in needed electronic
technology.
In the eighties and nineties, there was a renaissance in this area of research
with many proposed reconfigurable architectures developed in industry and
academia, such as: Matrix, Garp, Elixent, XPP, Silicon Hive, Montium, Pleiades,
Morphosys, PiCoGA. Such designs were feasible due to the constant progress of
silicon technology that let complex designs be implemented on one chip. The
world's first commercial reconfigurable computer, the Algotronix CHS2X4, was
completed in 1991. It was not a commercial success, but was promising enough
that Xilinx Inc. (the inventor of the Field-Programmable Gate Array (FPGA))
bought the technology and hired the Algotronix staff .
Current systems
Currently there are a number of vendors with commercially available
reconfigurable computers aimed at the high performance computing market;
including Cray, SGI and SRC Computers, Inc. . The reconfigurable computers are "Estrin"
hybrid computers with microprocessors that can be used in traditional CPU
cluster computers or coupled to user-programmable FPGAs for hybrid computing.
Cray supercomputer company (not affiliated with SRC Computers) acquired
OctigaBay and its reconfigurable computing platform, which Cray marketed as the
XD1 until recently. SGI sells the RASC platform with their Altix series of
supercomputers . SRC Computers, Inc. has developed a family of reconfigurable
computers based on their IMPLICIT+EXPLICIT architecture and MAP processor.
The XD1 and SGI FPGA reconfiguration can be accomplished either via the
traditional Hardware Description Languages (HDL), which can be generated
directly or by using electronic design automation (“EDA”) or electronic system
level (“ESL”) tools, employing high level languages like the graphical tool
Starbridge Viva or C-based languages like for example Handel-C from Celoxica,
DIME-C from Nallatech, Impulse-C from Impulse Accelerated Technologies or
Mitrion-C from Mitrionics.
In addition, Mitrionics has developed a Software Acceleration Platform that
enables software written using a single assignment language to be compiled and
executed on FPGA-based computers, such as those from Cray and SGI. The Mitrion-C
software language and Mitrion Virtual Processor enable software developers to
write and execute applications on FPGA-based computers in the same manner as
with other computing technologies, such as graphical processing units (“GPUs”),
cell-based processors, parallel processing units (“PPUs”), multi-core CPUs, and
traditional single-core CPU clusters.
SRC has developed a "Carte" compiler that takes an existing high-level languages
like C or Fortran, and with a few modifications, compiles them for execution on
both the FPGA and microprocessor. According to SRC literature, "...application
algorithms are written in a high-level language such as C or Fortran. Carte
extracts the maximum parallelism from the code and generates pipelined hardware
logic that is instantiated in the MAP. It also generates all the required
interface code to manage the movement of data to and from the MAP and to
coordinate the microprocessor with the logic running in the MAP." (note that SRC
also allows a traditional HDL flow to be used). The SRC systems communicate via
the SNAP memory interface, and/or the (optional) Hi-Bar switch.
Comparison of systems
As an emerging field, classifications of reconfigurable architectures are still
being developed and refined as new architectures are developed; no unifying
taxonomy has been suggested to date. However, several recurring parameters can
be used to classify these systems.
Granularity
The granularity of the reconfigurable logic is defined as the size of the
smallest functional unit (CLB) that is addressed by the mapping tools. Low
granularity, which can also be known as fine-grained, often implies a greater
flexibility when implementing algorithms into the hardware. However, there is a
penalty associated with this in terms of increased power, area and delay due to
greater quantity of routing required per computation. Fine-grained architectures
work at the bit-level manipulation level; whilst coarse grained processing
elements (rDPU) are better optimised for standard data path applications. One of
the drawbacks of coarse grained architectures are that they tend to lose some of
their utilisation and performance if they need to perform smaller computations
than their granularity provides, for example for a one bit add on a four bit
wide functional unit would waste three bits. This problem can be solved by
having a coarse grain array (rDPA) and a FPGA on the same chip.
Coarse-grained architectures (rDPA) are intended for the implementation for
algorithms needing word-width data paths (rDPU). As their functional blocks are
optimized for large computations they will perform these operations more quickly
and power efficiently than a smaller set of functional units connected together
with some interconnect, this is due to the connecting wires are shorter, meaning
less wire capacitance and hence faster and lower power designs. A potential
undesirable consequence of having larger computational blocks is that when the
size of operands may not match the algorithm an inefficient utilisation of
resources can result. Often the type of applications to be run are known in
advance allowing the logic, memory and routing resources to be tailored (for
instance, see KressArray Xplorer) to enhance the performance of the device
whilst still providing a certain level of flexibility for future adaptation.
Examples of this are domain specific arrays aimed at gaining better performance
in terms of power, area, throughput than their more generic finer grained FPGA
cousins by reducing their flexibility.
Rate of reconfiguration
Configuration of these reconfigurable systems can happen at deployment time,
between execution phases or during execution. In a typical reconfigurable
system, a bit stream is used to program the device at deployment time. Fine
grained systems by their own nature requires greater configuration time than
more coarse-grained architectures due to more elements needing to be addressed
and programmed. Therefore more coarse-grained architectures gain from potential
lower energy requirements, as less information is transferred and utilised.
Intuitively, the slower the rate of reconfiguration the smaller the energy
consumption as the associated energy cost of reconfiguration are amortised over
a longer period of time. Partial reconfiguration aims to allow part of the
device to be reprogrammed while another part is still performing active
computation. Partial reconfiguration allows smaller reconfigurable bit streams
thus not wasting energy on transmitting redundant information in the bit stream.
Compression of the bit stream is possible but careful analysis is to be carried
out to insure that the energy saved by using smaller bit streams is not
outweighed by the computation needed to decompress the data.
Host coupling
Often the reconfigurable array is used as a processing accelerator attached to a
host processor. The level of coupling determines the type of data transfers,
latency, power, throughput and overheads involved when utilising the
reconfigurable logic. Some of the most intuitive designs use a peripheral bus to
provide a coprocessor like arrangement for the reconfigurable array. However,
there have also been implementations where the reconfigurable fabric is much
closer to the processor, some are even implemented into the data path, utilising
the processor registers. The job of the host processor is to perform the control
functions, configure the logic, schedule data and to provide external
interfacing.
Routing/interconnects
The flexibility in reconfigurable devices mainly comes from their routing
interconnect. One style of interconnect made popular by FPGAs vendors, Xilinx
and Altera are the island style layout, where blocks are arranged in an array
with vertical and horizontal routing. A layout with inadequate routing may
suffer from poor flexibility and resource utilisation, therefore providing
limited performance. If too much interconnect is provided this requires more
transistors than necessary and thus more silicon area, longer wires and more
power consumption.
Tool flow
Generally, tools for configurable computing systems can be split up in two
parts, CAD tools for reconfigurable array and compilation tools for CPU. The
front-end compiler is an integrated tool, and will generate a structural
hardware representation that is input of hardware design flow. Hardware design
flow for reconfigurable architecture can be classified by the approach adopted
by three main stages of design process: technology mapping, placement algorithm
and routing algorithm. The software frameworks differ in the level of the
programming language.
Some types of reconfigurable computers are microcoded processors where the
microcode is stored in RAM or EEPROM, and changeable on reboot or on the fly.
This could be done with the AMD 2900 series bit slice processors (on reboot) and
later with FPGAs (on the fly).
Some dataflow processors are implemented using reconfigurable computing.
Paradigm shift
Table no. 1: Nick Tredennick’s Paradigm Classification Scheme Early Historic
Computers:
Programming Source
Resources fixed none
Algorithms fixed none
von Neumann Computer:
Programming Source
Resources fixed none
Algorithms variable Software (instruction streams)
Reconfigurable Computing Systems:
Programming Source
Resources variable Configware (configuration)
Algorithms variable Flowware (data streams)
It is called the Reconfigurable Computing Paradox, that by software to
configware migration (software to FPGA migration) speed-up factors by up to
almost 4 orders of magnitude have been reported, as well as the reduction of
electricity consumption by more than 1 order of magnitude - although the
technological parameters of FPGAs are are behind the Gordon Moore curve by about
4 orders of magnitude, and the clock frequency is substantially lower than that
of microprocssors. The reasons of this paradox are due to a paradigm shift, and
are also partly explained by the Von Neumann syndrome.
The fundamental model of the Reconfigurable Computing Machine paradigm, the
data-stream-based anti machine is well illustrated by the differences to other
machine paradigms that were introduced earlier, as shown by Nick Tredennick's
following classification scheme of computing paradigms (see "Table no. 1: Nick
Tredennick’s Paradigm Classification Scheme"):
The fundamental model of a Reconfigurable Computing Machine, the
data-stream-based anti machine (also called Xputer), is the counterpart of the
instruction-stream-based von Neumann machine paradigm. This is illustrated by a
simple reconfigurable system (not dynamically reconfigurable), which has no
instruction fetch at run time. The reconfiguration (before run time) can be
considered as a kind of super instruction fetch. An anti machine does not have a
program counter. The anti machine has data counters instead, since it is
data-stream-driven. Here the definition of the term data streams is adopted from
the systolic array scene, which defines, at which time which data item has to
enter or leave which port, here of the reconfigurable system, which may be
fine-grained (e. g. using FPGAs) or coarse-grained, or a mixture of both.
The systolic array scene, originally (early 80ies) mainly mathematicians, only
defined one half of the anti machine: the data path: the Systolic array (also
see Super Systolic Array). But they did not define nor model the data sequencer
methodology, considering that this is not their job to to take care where the
data streams come from or end up. The data sequencing part of the anti machine
is modeled as distributed memory, preferrably on chip, which consists of
auto-sequencing memory blocks (ASM blocks). Each ASM block has a sequencer
including a data counter. An example is the Generic Address Generator (GAG),
which is a generalization of the DMA.
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